Many processors have a cache. A cache is a block of memory for temporary storage of data that can be accessed by a processor more quickly than main memory. The cache array is typically indexed by a subset of the address bits and tagged with the remaining address bits. In a set-associative cache, each index in the cache can hold multiple memory locations. For example, a 4 way set-associative cache can hold 4 memory locations at each cache index. A typical set-associative cache has one or more arrays holding the tag values, referred to as the tagrams, and one or more arrays holding the data values, referred to as datarams. For fast access, it is common to implement each way of the data in a separate dataram.
In order to operate a processor at or near its peak performance, the tagrams and the datarams of a cache of a conventional processor are energized and accessed in parallel during each memory read and each memory write operation. Following each operation (e.g., in which a cache hit occurs), a selection process chooses the contents of one of the datarams of the cache and supplies this contents to the processor. The contents of the remaining datarams are disregarded.
While this conventional cache access technique works, energizing a tagram and multiple datarams during each memory read and each memory write operation of a processor wastes energy. What is needed are new techniques and means for accessing a cache that overcome the limitations associated with conventional cache access techniques and means.